The present invention is directed generally to digital video signal processing, and more particularly, to an on-screen display (OSD) processor for converting an image in 4:4:4 format to 4:2:2 format by mathematically combining at least two adjacent picture element values to produce a new value and using the new value for each of the at least two adjacent picture elements.
The MPEG-2 standard describes an encoding method that results in substantial bandwidth reduction by a subjective lossy compression followed by a lossless compression. The encoded, compressed digital data is subsequently decompressed and decoded in an MPEG-2 compliant decoder. Video decoding in accordance with the MPEG-2 standard is described in detail in commonly assigned U.S. Pat. No. 5,576,765, entitled xe2x80x9cVideo Decoderxe2x80x9d, which is hereby incorporated herein by reference in its entirety.
MPEG-2 video decoder/display chips are typically designed with a secondary display processor used for creating an overlay on the display. The source for the overlay image is coded overlay data that resides in the same memory that holds the MPEG video reference frames, input buffer, and user data storage. This secondary video, known in the industry as the on-screen display (OSD), is often used by a digital video system to convey information to a viewer such as television program schedules, viewing guide information, recording lists, headline news, sporting results, operational details, etc. When a customer is not viewing a full screen video program, the customer is probably interfacing with one of the OSD functions listed above.
On-Screen Display (OSD) arrangements employed in video processing systems include a switching (or xe2x80x9cmultiplexingxe2x80x9d) network for switching between graphic image representative signals and normal video signals so that a graphic image can be displayed on the screen of a picture reproduction device either in place of the image represented by the video signals or togther with (inserted in) the image. The graphic image can take the form of alphanumeric symbols or pictorial graphics, and can be used to indicate status information, such as channel numbers or time, or operating instructions.
Besides program video and audio quality, the OSD functions play a major part in a viewer""s perception of the overall quality of a digital video system. Thus, significant attention is given in the industry to the design and capabilities of the OSD features. This invention provides further enhancements to the conventional OSD processor and OSD features in order to establish commercial advantage of a digital video system employing the same.
This invention concerns a digital OSD arrangement for a digital video processing system, and especially one for digital video processing system in which the digital video signals represent image information in compressed form.
Briefly summarized, this invention comprises in one aspect a sub-system for a digital video decode system. The sub-system includes memory for receiving a graphics bitmap in 4:4:4 format. The graphics bitmap comprises a plurality of picture elements. The sub-system further includes an on-screen display processor coupled to the memory for converting the graphics bitmap in 4:4:4 format to graphics image words in 4:2:2 format. At least one graphics image word has a blended chrominance value obtained by merging chrominance values of at least two adjacent picture elements of the graphics bitmap. The blended chrominance value is obtained by mathematically combining corresponding chrominance values of the at least two picture elements merged to obtain the blended chrominance value.
In another aspect, a digital video signal processing system is provided which includes a video decoder for decoding a received sequence of encoded video data to form video image groups. Each video image group corresponds to two picture elements and includes a first luminance component corresponding to a first picture element of the two picture elements, a second luminance component corresponding to a second picture element of the two picture elements, and a pair of color difference components corresponding to each of the picture elements. The system further includes memory for storing on-screen display data comprising a graphics image. The on-screen display data is organized into graphics image groups. Each graphics image group corresponds to one picture element and includes a luminance component and two color difference components corresponding to the picture element.
An on-screen display processor is coupled to the memory for converting respective pairs of sequential graphics image groups stored in the memory to new graphics image groups. Each new graphics image group corresponds to two picture elements and includes a first luminance component corresponding to a first picture element of the two picture elements, a second luminance component corresponding to a second picture element of the two picture elements, and two blended color difference components corresponding to each of the picture elements. The two blended color difference components of each new graphics image group are produced by the on-screen display processor by respectively merging the two color difference components corresponding to the first picture element with the two color difference components corresponding to the second picture element comprising the pair of picture elements within the new graphics image group. The sub-system further includes a multiplexer which is responsive to the video image groups and to the new graphics image groups for selecting either the video image groups or the new graphics image groups to produce a sequence of resultant image groups. Each of the resultant image groups corresponds to two picture elements and includes a first luminance component corresponding to a first picture element of the two picture elements, a second luminance component corresponding to a second picture element of the two picture elements, and two blended color difference components corresponding to each of the two picture elements.
Processing methods and articles of manufacture encompassing the techniques of the above-outlined systems are also described and claimed herein.
To restate, an OSD processor is provided herein for a digital video decode system. This OSD processor has certain enhanced OSD capabilities. For example, an OSD processor in accordance with the principles of the present invention creates a more complex image without the need for using up colors in the limited space of an OSD color table (also known as CLUT). The resultant image has a xe2x80x9csofterxe2x80x9d look to it, without the hard edged colors created by the typical prior approach for converting from 4:4:4 to 4:2:2 format, i.e., by simply deleting every even or odd pixel""s chrominance pair. The softer image has the effect of reducing aliasing and sharp steps on angled lines within the displayed image. Also, within the world of graphics, when a single pixel-wide vertical line is to be represented, conversion from 4:4:4 format to 4:2:2 format using the above-noted prior art approach could make the image disappear if the image resides in a column that coincides with the pixel column having the deleted extra pair of chrominance values. Advantageously, an OSD processor implemented in accordance with the principles of the present invention employs chrominance merging or averaging thereby allowing a single pixel-wide vertical line of graphics data to be displayed irrespective of which pixel column the line is drawn in.